`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:37:57 05/04/2013
// Design Name:   InstructionDecoder
// Module Name:   T:/Lab3/tb_InstructionDecoder.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: InstructionDecoder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_InstructionDecoder;

	// Inputs
	reg pop_data;
	reg [7:0] data_in;

	// Outputs
	wire [3:0] data_out;
	wire [1:0] addr_out;
	wire ldr;
	wire sum;
	wire cmp;
	wire mul;

	// Instantiate the Unit Under Test (UUT)
	InstructionDecoder #(.N(4)) uut (
		.pop_data(pop_data), 
		.data_in(data_in), 
		.data_out(data_out), 
		.addr_out(addr_out), 
		.ldr(ldr), 
		.sum(sum), 
		.cmp(cmp), 
		.mul(mul)
	);

	initial begin
		// Initialize Inputs
		pop_data = 0;
		data_in = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		data_in <= 8'b01001111;
		pop_data <= 1'b1;
		
		#10;
		pop_data <= 1'b0;
		
		#90;
		data_in <= 8'b01010101;
		pop_data <= 1'b1;
	end
      
endmodule

